Fall 2000: Evolution of Copper Interconnect

Overview

Instructions

Organization

Teams

Results

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This has driven a fundamental change to copper-based metallurgy and low dielectric constant (low-K) materials as insulators, because copper (Cu) lowers the resistance of the wires and low-K dielectrics reduce the capacitance of the wires.  Together, these two materials and process changes reduce the interconnect delay time, i.e., the product of wire resistance and insulator capacitance.

The realities of these materials and process changes force other major changes in manufacturing.  First, the processes change dramatically.  For Cu-based metallurgy, this forces an emphasis on Cu electroplating, Cu chemical vapor deposition (CVD), and CVD of ultrathin barrier layers.  For low-K dielectrics, both spin-on wet chemical deposition and enhanced CVD are important candidates, with major challenges in their extendibility to increasingly lower K values, materials stability, and reliability.  Second, the new processes require development of new approaches to manufacturing equipment design, incorporating not only multichamber (multi-reactor) "cluster tools", but also fundamental advances in reactor design.  Third, the limitation of dry etch processes for Cu metallurgy has demanded a new strategy for process integration, namely Damascene processing, with profound consequences on equipment design and integration.  Implementing these profound changes in materials, processes, equipment, and integration has been a major focus of the National and International Technology Roadmap for Semiconductors.

With this backdrop, the instructor focused the technology domain of the course on key aspects of how the Cu Interconnect Revolution will evolve, not only in terms of the technology but primarily the systems-level aspects which determine the evolution.  The focal point became the transition from first-generation metallization strategy, including physical vapor deposition (PVD) of the barrier layer and Cu electroplating, to the expected all-CVD combination, including CVD of both barrier layer and Cu fill.  Much of the industry expects this transition to occur ultimately, but time scales and details are unclear.  However, it is clear that technology, manufacturing cost, and manufacturing efficiency will all steer the evolution of the Cu interconnect era.

The project emphasized materials and processes, equipment design and logistics, factory-level logistics, and cost-of-ownership considerations, as well as the overall development of the project itself.